Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs

The increasing size of modern field programmable gate arrays (FPGAs) allows for ever more complex applications to be mapped onto them. However, long design implementation times large designs can severely affect productivity. A modular methodology improve productivity in a divide and conqueror fashion but at the expense degraded performance power consumption resulting implementation. To reduce dominant dissipation component FPGAs, routing power, methodologies have been proposed that consider data communication between modules during module formation placement on FPGA. Selecting proper mapping region target other hand, is becoming critical process because heterogeneous resources column arrangements FPGAs. inappropriate FPGA regions could lead performance. Hence, we propose uses communication-aware placement, such are by selecting best shape factoring columnar resource arrangements. Additionally, techniques locking splitting deterministic convergence algorithm improved placement. This exhibits nearly 19% reduction with respect commercial CAD flows without any degradation achievable